In the fabrication of complex chips in which memory parts and digital/analog logic parts are fabricated simultaneously, it is very important to restrict the increase of additional processes while achieving desired characteristics of all necessary processes.
Currently, efforts to reduce manufacturing costs and to reduce consumption of electric energy via higher speed and higher integration of semiconductor devices are ongoing. In one line of effort, a System-On-Chip (SOC) device in which low-voltage device and high-voltage devices are included together in a single chip has been developed.
In an SOC device, although the characteristics of digital devices are important, the characteristics of analog devices, such as resistors, inductance coils, and capacitors, are particularly important. Methods of fabricating devices with higher levels of device integration by improving analog devices, particularly capacitors, are needed.
FIG. 1 is a sectional view illustrating the configuration of a related MIM capacitor. Referring to FIG. 1, the related MIM capacitor 1 may include a silicon (Si) semiconductor substrate 10, a first silicon insulating layer 20 and a lower metal layer 30 sequentially formed over the semiconductor substrate 10. A second silicon nitride (SiN) insulating layer 22 may be formed over the lower metal layer 30. Capacitor lower metal layers 40 and 42 may be sequentially formed over a portion of the second SiN insulating layer 22. A capacitor dielectric layer 24 may be formed over the capacitor lower metal layers 40 and 42. A capacitor upper metal layer 44 may be formed to overlap with the capacitor lower metal layers 40 and 42 with the capacitor dielectric layer 24 interposed therebetween. An insulating layer 26 may be formed over the entire surface of the capacitor dielectric layer 24 and the capacitor upper metal layer 44. Illustration of bonding metal layers, contact plugs, connection wirings, etc. formed on the metal layers of the MIM capacitor 1 may be omitted.
The MIM capacitor 1 having the configuration described above must include a capacitor dielectric layer 24 with a high dielectric constant to increase the level of integration of the device. Recently, an enhanced capacitor dielectric layer 24 with a higher dielectric constant has been required to provide capacitance densities in the range of about 2 fF/cm2 to 4 fF/cm2, and in extreme cases, higher than 4 fF/cm2.
To obtain a capacitance density of 4 fF/cm2 or more when the capacitor dielectric layer 24 is made of the most widely commercialized Plasma Enhanced Silicon Nitride (PE-SiN), the capacitor dielectric layer 24 must have a thickness of 30 nm or less.
However, a PE-SiN capacitor dielectric layer with a thickness of 30 nm or less results in abnormal deposition of SiN and deterioration in the reliability of the device. To overcome this problem, attempts may be made to form the dielectric layer using Al2O3 or HfO based materials instead of SiN. However, these materials require implementation of an Atomic Layer Deposition (ALD) process, with the inevitable generation of particles is due to inherent process characteristics.
Moreover, when the ALD process is performed using Al2O3 or HfO based materials, the overall fabrication method is complicated. A process for removing particles generated during the ALD process must be added. As a result, the complicated overall fabrication method exhibits low fabrication efficiency and disadvantageously increases the costs of the resulting semiconductor devices. To solve the above-described problems, a new configuration for a capacitor dielectric layer capable of improving fabrication efficiency and a method of fabricating the same are necessary.